In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical-mechanical planarization (CMP) is also a removal process used between levels. Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a “photoresist.” The photoresist is exposed by a “stepper,” a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist may be removed by plasma ashing.
Modification of electrical properties has historically consisted of doping transistor sources and drains, originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal, or in advanced devices, by rapid thermal anneal (RTA), which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).
Many modern chips have eight or more levels produced in over 300 sequenced processing steps. The raw wafer is engineered by at minimum, growth of an ultra-pure, defect-free silicon surface through epitaxy. In the most advanced logic devices, prior to silicon epitaxy, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a “straining step” wherein a silicon variant such as “silicon-germanium” (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called “silicon on insulator” technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of more idealized transistors with minimized parasitic effects.
Front end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complimentary electrical properties. In memory devices, storage cells (conventionally capacitors) are also fabricated at this time, either into the silicon surface or stacked above the transistor.
Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This process involves creating metal interconnecting wires that are isolated by insulating materials often referred to in the industry as dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently have dielectric constants around 2.7, although materials with constants as low as 2.2 are being offered to chipmakers.
Historically, the metal wires consisted of aluminum. In this approach to wiring often called “subtractive aluminum,” blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called “vias,” in the insulating material and depositing tungsten in them with a chemical vapor deposition (CVD) technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.
More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminum to copper and from the aforementioned silicon dioxides to newer low-K materials. This performance enhancement also comes at a reduced cost via “damascene” processing that eliminates processing steps. In damascene processing, in contrast to subtractive aluminum technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In “single damascene” processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire “lines” respectively. In “dual damascene” technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called Copper Barrier Seed (CBS), is a necessary evil to prevent copper diffusion into the dielectric. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest yet continuous barrier represents one of the greatest ongoing challenges in copper processing.
Current doping processes require photoresist or some other type of blocking layer to place dopant in only the desired regions of an IC wafer. Patterning of the photoresist or other type of blocking layer typically requires lithography steps before implantation and removal steps after implantation. In addition to adding considerable time to the overall process flow, lithography steps are expensive and the required removal steps may affect the overall process integration, for example, by removing finite amounts of field oxide.
Metal silicide thin films are integral parts of all microelectronics devices. They have been used as ohmic contacts, Schottky barrier contacts, gate electrodes, local interconnects, and diffusion barriers. With advances in semiconductor device fabrication technology, the shrinkage in line width continues at a fast pace. In the 90 nm generation devices produced in 2005, the gate length and thickness of silicide at the contact window were 32 nm and 20 nm, respectively. In the year 2007, it is predicted that for the 65 nm generation devices these numbers will decrease to 25 nm and 17 nm, respectively.
In addition, more transistors will be incorporated in one chip. However, owing to the demand for increased integration level, the surface area will not be adequate to meet the interconnect demand. Multi-level interconnections provide flexibility in circuit design and a substantial reduction in die size and, thus, chip cost.
For metallization of integrated circuit (IC) devices, transition metal suicides, including near-noble and refractory metal silicides, are used. The general requirements are: low resistivity; good adhesion to silicon; low contact resistance to silicon; appropriate Schottky barrier height or ohmic with heavily doped silicon (n+ or p+); thermal stability; appropriate morphology for subsequent lithography and etching; high corrosion resistance; oxidation resistance; good adhesion to and minimal reaction with SiO2; low interface stress, compatible with other processing steps such as lithography and etching, minimizing metal penetration; high electro-migration resistance; and formability at low temperature. The requirements are rather stringent and at present, only three suicides, TiSi2, CoSi2, and NiSi, are being considered for metal contacts for advanced devices.
PtSi and Pd2Si were used early on for metal contacts to lower the contact resistance of aluminum alloys as well as to serve as a diffusion barrier layer between aluminum alloy film and silicon. In the early 1980s, as the line-width decreased to about 1 μm, many refractory metal silicide films, such as MoSi2, WSi2, TiSi2, and TaSi2 were used by different manufacturers. For the 0.25 μm technology, TiSi2 was almost used exclusively. 3 For devices with line-width of 0.18 μm or smaller, TiSi2, CoSi2, and NiSi are possible candidate contact materials.
The usual steps to form a silicide begin with the cleaning of the wafers consecutively by organic solution, dilute hydrochloric acid (HF), and de-ionized water. The wafers are blown dry with a nitrogen gun or in a “spin-rinse-dry” process. An alternative is to dip the wafer in dilute HF then blow dry with a nitrogen gun or “spin dry.” The wafers are immediately placed in the metal deposition chamber and the surface is sputter-cleaned by argon ions if necessary (argon sputtering may cause particle issue). Next, metal thin films are deposited on silicon at room temperature or at a higher temperature, and finally, the wafers are heat treated either by traditional furnace annealing or by rapid thermal annealing to form silicides.
Prior to the deposition of metal thin films, a 1.5-nm to 2-nm-thick SiO2 layer was usually present at the silicon substrate surface following the etching of the thermal oxide. It is necessary for the contact metal layers to penetrate the thin oxide layer to react with the silicon to form silicides. Titanium and nickel atoms are capable of penetrating through the thin oxide. On the other hand, cobalt atoms have difficulty forming silicide with silicon if a thin oxide layer is present at the interface. An argon ion sputter-cleaning step is usually required. Since CoSi2 is widely used in devices with line-widths of 0.18 μm or smaller, the formation of CoSi2 is used as an example to illustrate the steps to form silicides on silicon. The deposition of cobalt thin films by sputtering is kept at room temperature. A mixture of Co2Si and CoSi is formed at 300° C. CoSi2 forms at 650° C. For rapid thermal annealing, the first-step and second-step annealing are conducted at 500-550° C. for 30-60 sec and 700-850° C. for 30-60 sec, respectively.
Silicidization is the process of forming a surface layer of a refractory metal silicide on silicon. A metal, today typically titanium or cobalt, is deposited on the silicon gate polysilicon and/or source drain regions and a layer of silicide (e.g., TiSi or CoSi) is formed when the two substances react at elevated temperatures.
Silicidization is a process that is also used to lower the resistance of the polysilicon interconnect and/or the source-drain contact and sheet resistances. In a “polycide” process, silicide is formed only on the polysilicon. In a “silicide” process silicide is formed on both the gate polysilicon and source-drain regions.
Silicides are widely used in semiconductor manufacturing for both logic and memory devices. On the same IC, silicides are used on different devices including both the poly on the gate regions and the source and drain. To optimize the process window or performance of different structures, it is desirable to apply different silicides with different thicknesses. However, silicide preference on the semiconductor structure are different and the present process flow can use only one metal deposition thickness as a trade-off for all devices.
Therefore, there is a need for a method for forming silicide layers using the same metal and having with different thicknesses over different areas of an IC wafer. There is also a need for a method for forming silicide layers using the different metals on different areas of an IC wafer.